This invention relates to an address conversion apparatus used in a computer system employing a microprocessor, and more particularly to an address conversion apparatus capable of efficiently converting from a logical address into a physical address.
In a computer system, the central processing unit outputs a logical address when executing a certain program or a process. Since this logical address merely indicates a virtual address on the program, when actually executing the program, this logical address must be converted into a physical address, that is, the address storing the instruction or data of the memory which stores the content of the practical instruction or data. It is the address conversion apparatus that converts from a logical address into a physical address.
FIG. 5 shows a block diagram of a translation lookaside buffer (TLB) as an address conversion apparatus for converting a logical address into a physical address in the conventional memory management system by paging.
This TLB is composed of a content addressable memory (CAM) 12 for storing the logical address 10 delivered from the CPU, a least recently used circuit (LRU) 14 for controlling the content thereof, and a random access memory (RAM) 18 being accessed by the CAM 12 and delivering a physical address 16. The CAM 12 possesses plural logical address storing parts 20 for storing plural logical addresses. In each logical address storing part 20, a valid bit 22 is provided, and depending on whether the valid bit 22 is 1 or 0, it is known whether the logical address stored in the corresponding logical address storing part 20 is valid (necessary) or invalid (unnecessary). The LRU 14 is composed of a number of least recently used counters 24 corresponding to the plural logical address storing parts 20, and these counters 24 and the logical address storing parts 20 are mutually linked by means of least recently used replace word wires 26 and content addressable memory word wires 28. The CAM 12 and the LRU 14 are joined by way of content addressable memory hit wires 30. The RAM 18 possesses physical address storing parts 32 corresponding to the logical address storing parts 20 of the CAM 12, and the logical address storing parts 20 and the physical address storing parts 32 are linked together by way of random memory access word wires 34.
Usually, when a certain process is executed by a processor, and its logical addresses are converted into physical addresses at a high speed ,by way of the TLB, the operation is effected according to the following procedure.
A certain logical address 10 is fed from the CPU to the CAM 12, and it compared with the logical address stored in the content addressable memory 12. Here, if a logical address coinciding with the input logical address 10 is present, the data corresponding to the physical address stored in the physical address storing part 32 of the RAM 18 corresponding to that logical address is delivered. As a result of this output of the data corresponding to the physical address, the data on that physical address is read out by the CPU or the processor, and is processed.
At the time of the above described logical address retrieval, if no coinciding logical address is present and the content addressable memory 12 is fully filled with the logical address data and it is necessary to delete the logical address data not required for the time being, the least recently used logical address storing part 20 is selected by the LRU 14, and the logical address data storing in that part is erased, and the data of the logical address to be used newly will be stored.
Thus, while a certain process is being executed, the input logical address 10 is converted at high speed by the TLB into an outputted physical address 16, but in the CAM 12 of the TLB, there was not field to recognize the process to be executed. Accordingly, when plural processes, that is, multiprocesses are executed in the processor, if a content switching occurs due to a change-over of the process to be executed, it is necessary to invalidate all data of the logical address newly in each process to update. This is because, even at the same logical address, if the process to be executed is different, the address content differs.
Furthermore, in the multiprocess environment, each process is scheduled, and the processor is used in time sharing, and therefore, in each process, it is necessary to update all logical addresses of the TLB every time changed over by the context switch until the process is completely terminated. Therefore, the system performance was lowered.